1. Field of the Invention
The invention relates to control apparatus in a stored program computer system and more particularly to such control apparatus where the computer operates in a non-overlap mode and still more particularly to such control apparatus where the instruction cycle for the computer system includes an instruction fetch cycle having at least more than one time state and an instruction execution cycle immediately following the instruction fetch cycle.
The present invention finds particular utility in small computer systems, where for cost reasons, parallel paths are not provided and thus the computer operates in a non-overlapped mode. In the non-overlapped mode, an instruction fetch cycle is followed by an instruction execution cycle. In the overlapped mode, execution of one instruction takes place while the next instruction is being fetched. The present invention enables variable length instruction fetch cycles so as to increase the overall efficiency of the computer system operating in the non-overlapped mode. whenever a branch instruction is encountered, the instruction fetch cycle of the branch to instruction is shortened by one time state. This time savings is significant because approximately 40% of the instructions in a non-overlapped computer system are branch instructions.
2. Prior Art
In the past, it has been the practice to have fixed length instruction fetch cycles. Improved performance was achieved by executing one instruction during the fetch of the next instruction. Such arrangements require dual registers for holding a pair of instructions and other additional data paths which are cost prohibitive in low cost computer systems.
In U.S. Pat. No. 3,766,527 an instruction execution cycle overlaps the instruction fetch cycle; however, the overlap is fixed and there is no variable length instruction fetch cycle.
The time for execution of branching operations is masked in U.S. Pat. No. 3,753,236 but more elaborate apparatus is required and the instruction fetch cycle is not variable. The execution of a high order micro instruction of a pair of micro instructions is overlapped with decoding of a low order branch instruction and the address preparation and fetch of the next pair of micro instructions. If a non-branch, low order instruction is encountered, it is transferred to the high order register for execution after the high order instruction is executed. In the present invention, only a single instruction is fetched and if it is a branch instruction, the address for the branch to address is set up during the execution of the branch instruction and the first time state of the instruction fetch cycle for the branch to instruction is skipped by selectively advancing the central processing unit (CPU) clock.